发明名称 Semiconductor integrated circuit equipment and its manufacture method
摘要 The object of the present invention is to suppress the increase of the contact resistance at the interface between the metal layer and the silicon plug in the wiring structure in which a metal layer is formed on and connected to a silicon plug. For its achievement, a lower semiconductor layer (drain) of a vertical-type MISFET is connected to an intermediate metal layer via an underlying plug composed of a polycrystalline silicon film, and a trap layer composed of a silicon nitride (TiN) film is formed on a part of the surface of the intermediate metal layer so as to surround the plug. The trap layer is formed in order to prevent an undesired high-resistance oxide layer from being formed at the interface between the plug and the intermediate metal layer.
申请公布号 US2005230716(A1) 申请公布日期 2005.10.20
申请号 US20050107888 申请日期 2005.04.18
申请人 RENESAS TECHNOLOGY CORP. 发明人 MORIYA SATOSHI;KIKUCHI TOSHIYUKI;KONNO AKIHIKO;SATO HIDENORI;YAMAMOTO NAOKI;MATSUOKA MASAMICHI;CHAKIHARA HIRAKU;NISHIDA AKIO
分类号 H01L23/522;H01L21/336;H01L21/768;H01L21/8234;H01L21/8244;H01L27/088;H01L27/092;H01L27/11;H01L29/76;(IPC1-7):H01L29/76 主分类号 H01L23/522
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