| 摘要 |
Some Gate Arrays and in particular Filed Programmable Gate Arrays (FPGAs), realize combinatorial logic by utilizing so-called "Look Up Tables" (LUTs). Unfortunaltely the circuit expenditure for a LUT is exponentially increasing with the number of inputs. The invention overcomes this problem by using a set of gates as AND, NAND, OR, NOR, XOR, XNOR, AND/OR combination gate, AND/NOR combination gate, OR/AND combination gate, OR/NAND combination gate, identity comparator between two vectors, multiplexer and adder. In addition, conventional GAs and FPGAs utilize routing structures and channels that allow a so-called Manhattan routing. This has the disadvantage that the signal delay on such a connection is highly dependent on the number of serially linked sections. Consequently, the delay time fluctuates significantly on different connections. The invention overcomes this problem by using a X/Y routing structure with a fixed number of connection points and a fixed local routing.
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