| 摘要 |
PROBLEM TO BE SOLVED: To provide a dither circuit capable of more efficiently reducing quantization noise in a quantizing device, particularly in a multi-stage analog-to-digital converter (ADC) 16. SOLUTION: A divide-by-3 circuit 12 generates a signal having a frequency of [sampling frequency]/3, from a sampling clock for ADC, and this signal is processed by a re-timing register 18 and a filter 14 to generate a dither signal. An adder 20 combines an analog signal to be digitized with the dither signal and supplies a resultant signal to the ADC 16. A cancellation signal is generated from a digital format signal of the dither signal by blocks 22, 24, 26, 28, 30, an adder circuit 32 combines the cancellation signal with a digital output signal of the ADC, and a corrected digital output signal having reduced quantization distortion is generated. COPYRIGHT: (C)2006,JPO&NCIPI
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