| 摘要 |
From layout information which was generated from a net list of a semiconductor integrated circuit, extracted are a critical path to guaranteed operating frequency and physical information such as wiring congestion and via density, and on the basis of the physical information, a place to be easily broken down is specified, and a critical path, in which a delay fault is envisaged, is sorted out from critical paths, and a test pattern is generated only as to the selected critical path. On that occasion, by use of automatic test pattern generation software, and by use of a weighting application verification model which is obtained from critical path sorting information based on physical information, a weighting factor of a critical path is given.
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