发明名称 Powerup control of PLL
摘要 An electronic device, such as a microprocessor, with a timing circuit. The timing circuit contains a phase locked loop that, during a first interval, checks whether a control signal in the phase locked loop is between a maximum allowed value and a minimum allowed value. When the control signal in the phase locked loop is above a maximum allowed value or below a minimum allowed value, the control circuit disables the phase locked loop for a second interval. When the control signal in the phase locked loop is below a maximum allowed value and above a minimum allowed value, the timing circuit indicates that the output of the phase locked loop is stable.
申请公布号 US6956416(B2) 申请公布日期 2005.10.18
申请号 US20040786584 申请日期 2004.02.25
申请人 ANALOG DEVICES, INC. 发明人 WILSON JAMES;LAHR LEW;PATTERSON STUART;BOYKO DANIEL
分类号 H03L3/00;H03L7/06;H03L7/095;H03L7/10;H03L7/18;(IPC1-7):H03L7/06 主分类号 H03L3/00
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