| 摘要 |
A storage element ( 100, 200 ) is capable of statically storing a dynamic input signal, and providing that static signal to dynamic logic gates. The element receives at least two input logic signals ( 150, 170 ), one of which is a dynamic signal ( 150 ) that may be one wire of a 1-of-N signal used in FAST14 logic from a dynamic logic gate ( 72 ) that may be a NDL gate, and generates one or more static logic output signals ( 190, 192 ). The element, which may or may not receive a clock signal ( 160 ), holds its outputs until its dynamic input ( 150 ) switches value on a subsequent evaluate cycle and at least one other input, which may be a write enable signal ( 170 ), changes signal value. In an alternative embodiment ( 200 ), the element may not change output values until a reset signal ( 330 ) is received during a prior clock cycle.
|
