发明名称 |
Structure and method for latchup suppression utilizing trench and masked sub-collector implantation |
摘要 |
A method and structure for an integrated circuit comprising a substrate of a first polarity; a trench structure in the substrate; a well region of a second polarity abutting the trench structure; and a heavily doped region of the second polarity abutting the trench structure, wherein the heavily doped region is adapted to suppress latch-up in the integrated circuit, wherein the heavily doped region comprises a sub-collector region, and wherein the trench structure comprises a deep trench structure or a trench isolation structure. The integrated circuit further comprises a p+ anode in the well region and a n+ cathode in the well region, wherein the integrated circuit is configured as a latchup robust p-n diode. In another embodiment, the integrated circuit further comprises a p+ anode in the well region; a n+ cathode in the well region; and a gate structure over the p+ anode and n+ cathode.
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申请公布号 |
US6956266(B1) |
申请公布日期 |
2005.10.18 |
申请号 |
US20040711300 |
申请日期 |
2004.09.09 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
VOLDMAN STEVEN H.;WATSON ANNE E. |
分类号 |
H01L21/762;H01L21/8238;H01L27/092;H01L29/76;H01L29/78;H01L29/94;H01L31/062;H01L31/113;H01L31/119;(IPC1-7):H01L29/76 |
主分类号 |
H01L21/762 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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