| 摘要 |
<p>A variable delay circuit wherein the delay amount per stage is large and can be easily varied. The variable delay circuit comprises a signal wire (P1) through which a pulse signal to be delayed is transmitted; input and output buffers (10,30) respectively provided at the input and output sides of the signal wire (P1); signal wires (P2,P3) disposed close to the signal wire (P1); and a delay setting pulse generation circuit (20) selectively applies, to the signal wires (P2,P3), a in-phase or anti-phase pulse signal synchronized with a timing at which to apply the pulse signal from the input buffer (10) to the signal wire (P1).</p> |
