发明名称 SEMICONDUCTOR DEVICE AND TESTING METHOD
摘要 PROBLEM TO BE SOLVED: To provide a semiconductor device in which the error of an uncorrectable pattern is corrected by adding the already uncorrectable pattern and one-bit fail bit, and to provide a testing method. SOLUTION: A memory LSI comprising a product code ECC circuit comprises a means for solely operating one of first and second codes of a product code, respectively in a test mode. In the case of encoding using one of the first and second codes of the product code, based on inputted control signals TCODE1, TCODE2, data in a memory 10 are inputted to one of first and second encoder circuits 201 and 202, an encoded output from said encoder circuit is inputted to a parity generation circuit 31, a generated parity is written into the memory 10, one of the first and second codes is read out from the memory 10 and inputted to one of first and second decoder circuits 203 and 204, an output of said decoder circuit is supplied to a syndrome arithmetic circuit 32 to perform a correcting operation, and a corrected bit is written in the memory. COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2005285270(A) 申请公布日期 2005.10.13
申请号 JP20040100579 申请日期 2004.03.30
申请人 ELPIDA MEMORY INC 发明人 TOHO YOSHIROU;ITO YUTAKA
分类号 H03M13/01;G06F11/00;G06F11/10;G11C11/401;G11C11/406;G11C11/4078;G11C29/00;G11C29/42;H03M13/00;H03M13/29;(IPC1-7):G11C29/00 主分类号 H03M13/01
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