发明名称 STORAGE DEVICE SYSTEM
摘要 PROBLEM TO BE SOLVED: To eliminate an LSI pin neck and a package connector neck when connecting a plurality of processors and an external memory. SOLUTION: A memory control unit 195 is comprised of a plurality of selector groups 190, shared memories 160a, 160b connected by a shared memory path 165, and cache memories 170a, 170b, each selector group 190 includes four MP sections 110, two SM selectors 140, and two CM selectors 150, and each MP section 110 includes a processor, an LM (local memory) 114, an SM access circuit 113, a CM access circuit 112, and a buffer 115. The number of paths from each SM selector to the shared memories 160a, 160b is then made less than the number of paths from the plurality of MP sections to each SM selectors, and the number of paths from each CM selector to the cache memories 170a, 170b is made less than the number of paths from the plurality of MP sections to each CM selector. COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2005285139(A) 申请公布日期 2005.10.13
申请号 JP20050128856 申请日期 2005.04.27
申请人 HITACHI LTD 发明人 YAMAKAMI KENJI;FUJIMOTO KAZUHISA;KUROSU YASUO;HONMA HISAO
分类号 G06F12/08;G06F12/06;G06F12/16;G06F13/16;(IPC1-7):G06F12/06 主分类号 G06F12/08
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