发明名称 LOGIC GENERATION METHOD OF INTEGRATED CIRCUIT AND LOGIC GENERATION PROGRAM OF INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To shorten the logic design period of an integrated circuit by preventing connection mistakes of wiring and description mistakes when designing a logic. SOLUTION: In order to connect an IO cell to be connected to an external terminal, to a logic circuit, connection specifications of terminals of the IP cell and terminals of the logic circuit are inputted from the outside and circuit elements are automatically inserted between the IO cell and the logic circuit in accordance with the connection specifications. Then connection relations of elements constituting the integrated circuit are extracted to generate a netlist. Therefore, required circuit elements are surely inserted between the IO cell and the logic circuit in accordance with the connection specifications. COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2005284893(A) 申请公布日期 2005.10.13
申请号 JP20040100102 申请日期 2004.03.30
申请人 FUJITSU LTD 发明人 IWAMOTO MASAMI;WATANABE GYOJI;KOMURA MAYUMI;SATO TETSUYA;SUZUKI NORIFUMI;NAKABAYASHI SEIJI
分类号 G06F17/50;H01L21/82;(IPC1-7):G06F17/50 主分类号 G06F17/50
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