发明名称 Digital frequency synthesis clocked circuits
摘要 Embodiments of the invention may include a reference input port to receive a reference clock, the reference clock being based on a bypass clock, a feedback input port to receive a feedback clock from a clocked circuit, and logic to compare the reference clock and the feedback clock and to generate an output based on the comparison.
申请公布号 US2005229066(A1) 申请公布日期 2005.10.13
申请号 US20040815500 申请日期 2004.03.31
申请人 WOLFF NEAL;LIM CHEE H 发明人 WOLFF NEAL;LIM CHEE H.
分类号 G01R31/28;G06F11/00;(IPC1-7):G06F11/00 主分类号 G01R31/28
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