| 摘要 |
PROBLEM TO BE SOLVED: To solve the problem that a manufacturing margin is small and when the distance between source/drain wiring is made short, yield is lowered, in the conventional manufacturing method wherein the number of manufacturing steps is reduced by forming a semiconductor layer and the source/drain wiring of a channel etching type and insulating gate type transistor are formed in one photo etching step using a halftone exposure technique. SOLUTION: A four mask process plan by which the halftone exposure technique is not needed is constructed by forming the source/drain wiring of the etching stop type and insulating gate type transistor using a photosensitive organic insulating layer to leave the photosensitive organic insulating layer as it is in addition to the rationalization that scanning lines and pseudo pixel electrodes consisting of a laminated layer of a transparent conductive layer and a metal layer are simultaneously formed, the metal layer on the pseudo pixel electrodes is removed when aperture parts to a gate insulating layer are formed and transparent conductive pixel electrodes are formed. COPYRIGHT: (C)2006,JPO&NCIPI |
