| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a data processor preventing HARQ synthesis and rate dematching from competing for memory access during an HARQ process that uses two or more memories. <P>SOLUTION: A buffer 2 comprises two physical memories 21, 22, one of which is used as a memory for even-numbered addresses, and the other of which is used as a memory for odd-numbered addresses. Also, access to the buffer 2 by HARQ synthesis and rate dematching is controlled so that when the HARQ synthesis accesses the memory for even-numbered addresses, the rate dematching accesses the memory for odd-numbered addresses. <P>COPYRIGHT: (C)2006,JPO&NCIPI</p> |
