| 摘要 |
An automatic frequency correction phase-locked loop (PLL) circuit includes an analog control circuit and a digital control circuit. The digital control circuit includes a High-side comparator and a Low-side comparator which receive an analog control voltage, a state monitor circuit, and a counter and decoder circuit. At least one of the High-side comparator and the Low-side comparator includes a threshold switching circuit which selectively gives a first threshold and a second threshold having different. When the analog control voltage remains between the High-side threshold and the Low-side threshold in a state in which the threshold switching circuit gives the first threshold, the threshold switching circuit switches the first threshold to the second threshold and expands the interval between the High-side threshold and the Low-side threshold.
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