发明名称 TEST TERMINAL NULLIFICATION CIRCUIT
摘要 <P>PROBLEM TO BE SOLVED: To prevent the invasion into an unjust test mode from a test terminal by nullifying the test terminal with a simple circuit structure. <P>SOLUTION: The nullification circuit comprises a switch circuit 102 for making test signal input from a test terminal 101 effective as it is or specific non-effective state and outputting to a test objective circuit 106, a test signal control circuit 105 for controlling the effective or non-effective state of the output signal to the switch circuit 102, a test mode signal generation circuit 103 for generating test mode signal indicating the output signal of the switch circuit 102 effective state, and a nullification signal generation circuit 104 formed by using electrically rewritable non-volatile memory element which is capable of outputting the nullification signal compulsorily making the output signal of the switch circuit 102 non-effective state. The test signal control circuit 105 receives input of the nullification signal and if receives the input of the test mode signal, it does not make the output signal of the switch circuit 102 effective state. <P>COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2005283208(A) 申请公布日期 2005.10.13
申请号 JP20040094572 申请日期 2004.03.29
申请人 SHARP CORP 发明人 FUKUHARA CHIKAO
分类号 G01R31/28;G01R31/317;G01R31/3185;G06F21/02;G06K19/07;G11C29/02 主分类号 G01R31/28
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