High speed CMOS flip-flops and clocked logic gates

摘要

A fast CMOS flip-flop comprises first and second cascade-connected latch stages each with an input section having only two NMOS transistors in series, thereby allowing rapid discharge of the nodes N301 and N304. The first and second input sections comprise transistors 301-303 and 304-306 respectively. The clock pulse CKP is narrow. Alternative circuits using a second clock signal are disclosed (figure 9). Clocked logic gates based on the fast flip-flops are disclosed (e.g. figures 6 and 11).