| 摘要 |
An apparatus and method for compensating clock period elongation during scan testing in an integrated circuit, IC, comprises operating a clock associated with the IC at a frequency, fTARGET, at which IC operation is sought to be determined, measuring the actual clock period, TCLOCK_OUT, at a clock output, scan testing the IC, measuring the actual clock period, TSCAN_CLOCK_OUT, at the clock output, determining a delay by calculating the difference between TSCAN_CLOCK_OUT and TCLOCK_OUT, and compensating for the delay by increasing the clock frequency during scan test. <IMAGE>
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