发明名称 Delay circuit with reduced Vdd dependence and semiconductor memory device having the same
摘要 <p>The delay circuit has a voltage source which supplies voltage to a delay chain comprising a pair of inverters (401,404), transistors (406,407), resistor (402), NAND gate (405) and capacitors (403,408), in response to the input signal (IN). Independent claims are also included for the following: (1) delay circuit arrangement; and (2) delay circuit manufacturing method.</p>
申请公布号 KR100521360(B1) 申请公布日期 2005.10.12
申请号 KR20020019951 申请日期 2002.04.12
申请人 发明人
分类号 G11C8/00;G11C8/18;H03K5/08;H03K5/13;H03K5/1534;(IPC1-7):G11C8/00 主分类号 G11C8/00
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