| 摘要 |
This invention relates to an IP processor, and more particularly, provides an IP processor that reduces network load when a plurality of IP processors connected to ATM switches are used in edge portion of an IP network. The IP processor is comprised of a line interface unit for interfacing with an ATM switch, an IP packet buffer unit for temporarily storing an IP packet from the line interface unit, and sending out the IP packet after address resolution to the line interface unit, and an IP address resolution unit that responds to address resolution request from the IP packet buffer unit and returns the destination address information after address resolution, wherein the IP packet buffer unit sends out, when destination address information cannot be retrieved from the IP address resolution unit, the temporarily stored IP packet to a transfer route for direct transfer between IP processors.
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