发明名称 |
Error detection in dynamic logic circuits |
摘要 |
Error detection apparatus and methods for dynamic logic are provided. Circuit errors are detected by comparing true and complement signals to ensure they are in fact complementary signals. A pseudocomplement technique is used to implement an adder in which distinct logic cones generate the true and complement carry signals. Other embodiments comprising additional features, such as shared logic cone decomposition, are also provided.
|
申请公布号 |
US6954912(B2) |
申请公布日期 |
2005.10.11 |
申请号 |
US20020150847 |
申请日期 |
2002.05.17 |
申请人 |
FUJITSU LIMITED |
发明人 |
SRIVASTAVA PRANJAL;NAINI AJAY;DHABLANIA ATUL |
分类号 |
G06F11/18;G01R31/317;G01R31/3183;G01R31/3185;H03K19/096;(IPC1-7):G06F17/50 |
主分类号 |
G06F11/18 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|