发明名称 Semiconductor memory device
摘要 A first level metal interconnection line in a layer below a third level metal interconnection line serving as a main word line MWL is used as a shunting interconnection line and electrically connected to a first level polysilicon interconnection line constituting a sub word line SWL at prescribed intervals. By applying a hierarchical word line structure and a word line shunting structure both, a word line is driven into a selected state at high speed without increasing an array occupancy area and manufacturing steps.
申请公布号 US6953960(B2) 申请公布日期 2005.10.11
申请号 US20010996574 申请日期 2001.11.30
申请人 RENESAS TECHNOLOGY CORP. 发明人 TOMISHIMA SHIGEKI
分类号 G11C11/407;G11C5/06;G11C8/14;G11C11/401;G11C11/408;H01L21/8242;H01L27/108;(IPC1-7):H01L27/108;H01L29/76;H01L29/94;H01L31/119;H01L29/788 主分类号 G11C11/407
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