发明名称 |
Marking in history table instructions slowable/delayable for subsequent executions when result is not used immediately |
摘要 |
After an instruction loads data into a register at a first time, the register is monitored to see if it is read in a next clock cycle. When the data is not read in the next clock cycle, the instruction is classified as a slowable instruction. An instruction address associated with the instruction is used to update a history table. The history table stores information to indicate if an instruction is a slowable instruction or a non-slowable instruction. When the instruction address of the instruction is encountered at a second time, the history table is used to determine if the instruction is slowable or non-slowable.
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申请公布号 |
US6954848(B2) |
申请公布日期 |
2005.10.11 |
申请号 |
US20020038038 |
申请日期 |
2002.01.02 |
申请人 |
INTEL CORPORATION |
发明人 |
RAKVIC RYAN;WILKERSON CHRISTOPHER;BLACK BRYAN;GROCHOWSKI EDWARD;SHEN JOHN;BREKELBAUM EDWARD |
分类号 |
G06F9/00;G06F9/30;G06F9/38;(IPC1-7):G06F9/30 |
主分类号 |
G06F9/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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