发明名称 DSRC communication circuit and communication method
摘要 A DSRC communication technology that prevents unique word detection errors even when the frame changes in data reception and the timing of the unique word detection window and the timing of the received data do not match, and that adjusts the data transmission timing in a flexible fashion when the slot timing deviates from the frame timing. In this technology, bit counter 111 generates the frame timing from the frame synchronization signal, and bit counter 112 generates the sot timing in response to the slot synchronization signal. The unique word detection window is generated from the frame timing and the received data operation timing and the data reception timing are generated from the slot timing. In addition, the data transmission timing and the transmission data operation timing are generated based on one of the frame timing and the slot timing chosen in selector 123.
申请公布号 US2005220150(A1) 申请公布日期 2005.10.06
申请号 US20050095669 申请日期 2005.04.01
申请人 MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. 发明人 OYAMA SHIGEKI
分类号 G07B15/00;H04J3/00;H04J3/06;H04L7/00;H04L7/08;(IPC1-7):H04J3/06 主分类号 G07B15/00
代理机构 代理人
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