| 摘要 |
A bipolar differential input stage with an input bias current cancellation circuit comprises an input pair (Q1, Q2) and a bipolar tracking transistor (Q3). The input stage is arranged such that the collector currents in the input pair (Q1, Q2) and tracking transistor (Q3), and the collector-emitter voltages of the input pair (Q1, Q2) and tracking transistor (Q3), are substantially equal. A lateral PNP transistor's (Q7) first collector provides the tracking transistor (Q3) base current required to achieve the substantially equal collector current, and second and third collectors (Q7) provide copies of the tracking transistor (Q3) base current as bias current cancellation currents to the bases of the input pair (Q1, Q2), thereby reducing the input stages' input bias currents. |
