| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor memory which suppresses variance in position of a carrier storage part so that the carrier storage part is always formed nearby both ends of a gate insulating film with small variance in position even if there is variance in drain voltage or impurity region structure due to variance of manufacturing stages. SOLUTION: Provided are a 1st gate electrode 4 arranged on a 1st gate insulating film 3 where carriers are accumulated and a 2nd gate electrode 5, which is capacitively coupled with the 1st gate electrode, on both sides of it. When a write voltage is applied to one of the 1st and 2nd gate electrodes, a voltage is induced at the other gate electrode in a floating state and hot carriers are injected within a narrow range nearby the boundary to perform writing operation. Impurity regions 2-1 and 2-2 as a source and a drain are formed apart from the 1st gate electrode. The 1st gate electrode can be replaced with a high-dielectric film. COPYRIGHT: (C)2006,JPO&NCIPI
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