发明名称 |
Pipeline module circuit structure with reduced power consumption and method of operating the same |
摘要 |
A pipeline module circuit structure with reduced power consumption and a method for operating the pipeline module circuit structure are provided. The pipeline module circuit structure comprises a plurality of pipeline stages and a clock generator, each of the pipeline stages connected to adjacent pipeline stages through a bus. A clock controller is installed in each of the pipeline stages, so as to set the clock frequency of a preceding pipeline stage to an idle frequency or stop when a present pipeline stage starts to operate and to set the clock frequency of a next pipeline stage to an operation frequency when the present pipeline stage is about to cease, such that the power consumption of the pipeline module circuit structure is effectively reduced.
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申请公布号 |
US2005223262(A1) |
申请公布日期 |
2005.10.06 |
申请号 |
US20050140902 |
申请日期 |
2005.06.01 |
申请人 |
CHEN YUNG-HUEI;HUANG HSIANG-CHOU;HU CHIH-WEI |
发明人 |
CHEN YUNG-HUEI;HUANG HSIANG-CHOU;HU CHIH-WEI |
分类号 |
G06F1/32;(IPC1-7):G06F1/04 |
主分类号 |
G06F1/32 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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