发明名称 ON-CHIP DECOUPLING CAPACITOR INSERTION METHOD AND INTEGRATED CIRCUIT DEVICE
摘要 PROBLEM TO BE SOLVED: To make it possible to arrange sufficient amount of capacitors by preventing the interference between the wiring of an on-chip decoupling capacitor cell and the common wiring of an integrated circuit, while satisfying the performance of the integrated circuit. SOLUTION: When an on-chip decoupling capacitor cell is inserted into an integrated circuit, it is detected whether the wiring in this cell and the general signal wiring of an integrated circuit short-circuit, and in case of short-circuiting, another on-chip decoupling capacitor cell 7 is used. This cell 7 uses a first metal layer of for a wiring 8 of a lateral direction, and a second metal layer for a wiring 9 of a longitudinal direction, and the wiring 8, 9 are connected via a contact 10. Since a general signal wiring 5 exists in the same first metal as the wiring 8, it is possible to avoid a short circuit with a wiring 9 of the second metal layer. COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2005276970(A) 申请公布日期 2005.10.06
申请号 JP20040086072 申请日期 2004.03.24
申请人 NEC CORP 发明人 GOTO TAKASHI
分类号 H01L27/04;H01L21/82;H01L21/822;H01L27/118;(IPC1-7):H01L21/82 主分类号 H01L27/04
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