LOGICAL CIRCUIT, AND SYSTEM, METHOD, AND PROGRAM FOR DESIGNING LOGICAL CIRCUIT

摘要

PROBLEM TO BE SOLVED: To provide a latch circuit constituting a high-speed pipeline. SOLUTION: The latching circuit is prepared by which a latch circuit with a high-speed through-delay is obtained by being added to a basic logical circuit. Then a means is provided which obtains a latch circuit position to maximally absorb the deviation of a clock edge such as skew or jitter, and constitutes the latch circuit by adding the latching circuit to the basic logical circuit which is positioned at an obtained point. Accordingly, the latch circuit is designed which is not maximally affected by the skew or the jitter. COPYRIGHT: (C)2006,JPO&NCIPI