发明名称 Converter containing time sequence
摘要 A design method for solid state converters. Denial and give up self excited converter, adopt only separate excited converter, start-stop operation of the output stage is so arranged by special means that the control voltage does earlier to start actuating and later to stop in comparing with the main loop being power switched on and off. Or put a frequent switch on the main loop, keeping control voltage non-stop actuating.
申请公布号 US2005218724(A1) 申请公布日期 2005.10.06
申请号 US20050092951 申请日期 2005.03.30
申请人 ZHANG ZHIPING 发明人 ZHANG ZHIPING
分类号 H02J1/00;H02M1/00;H02M1/08;H02M1/36;(IPC1-7):H02J1/00 主分类号 H02J1/00
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