发明名称 METHODS AND APPARATUS FOR MODULAR REDUCTION CIRCUITS
摘要 Techniques are provided for performing modular arithmetic on a key composed of many bits. One circuit implementation includes a distributor (610), one or more lookup tables (630A, 630B and 630C) and a plurality of adders (620 and 650). The distributor segments the key into a plurality of partitions. Each partition is based on a polynomial expression corresponding to a fixed key size. Each of the bits contained within the partitions are routed on a partition basis to one or more lookup tables, the routed bits acting a indices into the one or more tables. The lookup tables store precomputed values based upon the polynomial expression. The outputted precomputed values from one or more lookup tables are outputted to the plurality of adders. The plurality of adders add the bits from a portion of the routed partitions and the outputted precomputed values from the one or more lookup tables to form the binary residue.
申请公布号 WO2005024583(A3) 申请公布日期 2005.10.06
申请号 WO2004US28710 申请日期 2004.09.02
申请人 ISIC CORPORATION;STOJANCIC, MIHAILO, M. 发明人 STOJANCIC, MIHAILO, M.
分类号 G11C7/10;G11C15/00 主分类号 G11C7/10
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