发明名称 SYSTEM AND METHOD FOR DESIGNING TEST FACILITATION CIRCUIT, AND PROGRAM
摘要 PROBLEM TO BE SOLVED: To provide a test facilitation circuit designing method with which a scan chain having an equalized length can be easily constructed. SOLUTION: A test facilitation circuit designing method according to the present invention includes the steps of: acquiring the number of scan chains to be constructed, the number of flip-flops for each of a plurality of logic blocks; determining the number of flip-flops which are equal for each scan chain; constructing a scan chain by connecting an input terminal and an output terminal using the equal number of flip-flops selected from one logic block; and constructing a scan chain by connecting an input terminal and an output terminal using the equal number of flip-flops selected from the one logic block and another logic block. COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2005276069(A) 申请公布日期 2005.10.06
申请号 JP20040091856 申请日期 2004.03.26
申请人 NEC ELECTRONICS CORP 发明人 SASAKI TAKESHI
分类号 G01R31/28;G06F17/50;H01L21/822;H01L27/04;(IPC1-7):G06F17/50 主分类号 G01R31/28
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