| 摘要 |
PROBLEM TO BE SOLVED: To relieve the electric field of an offset drain while suppressing the reduction of an effective channel width. SOLUTION: An n-type elevated offset drain layer 7a connected to an n-type offset drain layer 6 is laminated upon a drain-side p-type semiconductor layer 2 in a state where a side wall 10b is separated from a gate electrode 4 and circular p-type isolated patterns 7b, which are arranged on the surface of the nn-type elevated offset drain layer 7a in a state where the patterns 7b are separated from each other, and, at the same time, the depths of which are set to reach the p-type semiconductor layer 2. The p-type isolated patterns are formed in the n-type elevated offset drain layer 7a. COPYRIGHT: (C)2006,JPO&NCIPI
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