发明名称 |
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE |
摘要 |
<p>A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.</p> |
申请公布号 |
KR20050096863(A) |
申请公布日期 |
2005.10.06 |
申请号 |
KR20050076726 |
申请日期 |
2005.08.22 |
申请人 |
KABUSHIKI KAISHA HITACHI SEISAKUSHO(D/B/A HITACHI, LTD.) |
发明人 |
OKUDA YUUICHI;KOKUBO MASARU;NAKAGOME YOSHINOBU;YAHATA HIDEHARU;MIYASHITA HIROKI |
分类号 |
G11C11/407;G11C7/10;G11C7/22;G11C11/401;G11C11/4074;G11C11/4076;H01L21/76;H01L21/822;H01L21/8242;H01L27/04;H01L27/10;H01L27/108;H03K5/13;H03K5/131;H03L7/00;H03L7/081;H03L7/089;H03L7/107;(IPC1-7):H01L27/10 |
主分类号 |
G11C11/407 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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