| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a digital phase lock loop circuit in which a time elapsing before the settling of an internal clock signal is shortened by a simple arrangement, and fluctuation can be reduced after the settling. <P>SOLUTION: A comparing section 113 compares phases of an external clock signal and an internal clock signal to detect a time difference and a phase difference. When the time difference and the phase difference are outputted as control signals for a voltage controlled crystal oscillator 12, a correction value corresponding to the peak value of the control signal is read out from a memory 114. After the correction value is multiplied by a constant coefficient and the absolute value is reduced, the correction value is added to the peak value of the control signal and corrected. <P>COPYRIGHT: (C)2006,JPO&NCIPI |
