发明名称 VIDEO CAPTURE CIRCUIT AND VIDEO CAPTURE METHOD
摘要 PROBLEM TO BE SOLVED: To provide a video capture circuit and a video capture method which prevents discontinuity, flickers, etc. of videos resulting from the deviation of VSYNC/HSYNC on the writing side and the reading side, based on the difference in the frequency between the writing clock and the reading clock. SOLUTION: A vertical synchronizing signal VSYNC<SB>R</SB>for reading, synchronized with a reading clock CL2, is generated in the video capture circuit; the phase difference between a vertical synchronizing signal VSYNC<SB>W</SB>synchronized with a writing clock CL1 and the vertical synchronizing signal VSYNC<SB>R</SB>for reading is monitored in a phase synchronization control part 14; and a period of the vertical synchronizing signal VSYNC<SB>R</SB>for reading is controlled, based on the phase difference. COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2005275242(A) 申请公布日期 2005.10.06
申请号 JP20040091523 申请日期 2004.03.26
申请人 ALPINE ELECTRONICS INC 发明人 TEZUKA KAZUTO
分类号 H04N5/12;G09G5/00;G09G5/12;G09G5/18;G09G5/36;G09G5/377;G09G5/397;G09G5/399;(IPC1-7):G09G5/12 主分类号 H04N5/12
代理机构 代理人
主权项
地址