Phase locked loop frequency synthesizer

摘要

The phase locked loop frequency synthesizer, includes: an LC-tank circuit which includes an inductor and a variable capacitor in which the capacity changes depending on the input voltage; a group of fixed-value capacitors which is connected to the LC-tank circuit in parallel; a voltage control oscillating unit which outputs a signal with a frequency determined by the LC-tank circuit and the group of fixed-value capacitors; a phase control unit which generates an output current based on an error operator between a first signal with a divided frequency of a reference frequency and a second signal with a divided frequency of the frequency output from the voltage control oscillating unit; a fixed-value capacitor controlling unit which outputs a selection signal which determines the combination of the fixed-value capacitors to be connected to the LC-tank circuit in parallel based on a frequency dividing ratio setting signal including information about dividing ratio of the second signal, and controls the connection of the fixed-value capacitors selected from the group of fixed-value capacitors based on the selection signal to the LC-tank circuit in parallel; and a variable capacitor controlling unit which selects either one of a fixed bias voltage and the voltage obtained by converting the output current output from the phase control unit and inputs the selected voltage to the variable capacitor of the LC-tank circuit.