摘要 |
<p>The described analog-digital converter comprises quantization means (DAC, COMP) having an input for receiving an analog quantity to be converted (VIN), a register (REG) having an output (OUTBUS) for providing a digital quantity corresponding to the analog quantity, a timing pulse generator (CLK-GEN) and logic means (LOG) connected to the quantization means (DAC, COMP), the register (REG) and the timing pulse generator (CLK-GEN) and capable of responding to a conversion request signal (CONVREQ) by activating the quantization means in such a manner as to make them carry out predetermined operations timed by the timing pulses and load into the register (REG) the digital quantity to be provided at the output (OUTBUS).</p><p>With a view to permitting the converter to function even when a system clock is not available, the timing pulse generator (CLK-GEN), which is incorporated in the integrated circuit that comprises the rest of the converter, comprises an oscillator capable of being started/stopped by a binary signal applied to its activation input (STOP) and the logic means are capable of generating a stop signal (RESOSC) of the oscillator and comprise means (MONOST, OR) for generating the binary signal to be applied to the activation input (STOP) of the oscillator (CLK-GEN). This signal assumes a first or a second binary state corresponding, respectively, to activation and deactivation of the oscillator in response to, respectively, the conversion request signal (CONVREQ) and the stop signal (RESOSC) of the oscillator.</p> |