Low consumption and low noise analog-digital converter of the SAR type and method of employing it

摘要

The described converter comprises switched-capacitor quantization means (DAC, COMP) for receiving an analog quantity to be converted (VIN), a register (REG) for a digital quantity corresponding to the analog quantity, a timing pulse generator (CLK-GEN) and logic means (LOG) capable of responding to a conversion request signal (CONVREQ) by activating the quantization means in such a way that they will carry out predetermined operations timed by the timing pulses and load in the register (REG) the digital quantity to be furnished as output (OUTBUS). With a view to saving electric energy during the conversion and reducing the noise induced by the generator, the generator (CLK-GEN) comprises means for modifying the duration and/or the frequency of the timing pulses in response to regulation signals (REGBUS0, REGBUS1) emitted by the logic means.

Also described is a method of using the converter that comprises the following phases: loading of the analog quantity (VIN) in the quantization means (DAC, COMP), memorization of the loaded analog quantity and identification in the course of successive attempts in accordance with SAR technique of the bits of the digital code corresponding to the analog quantity to be converted. The duration and/or the frequency of the timing pulses are modified during at least one of the phases indicated above in response to regulation signals emitted by the logic means (LOG).