Clock multiplying delay-locked loop for data communications

摘要

In a communications system, data is multiplexed onto a transmission medium at a transmitter and demultiplexed from the transmission medium at a receiver. The clock applied to the transmitter and receiver is a multiplying delay-locked loop in which a delay line provides a multiplied clock which is applied back to its input. A delay adjustment circuit including a proportional phase comparator of low offset adjusts delay in the delay line.