| 摘要 |
The present invention is constructed of a first input circuit having a higher logic level V<SUB>IH </SUB>made up of a first inverter circuit 22 controlled by an input signal and an N-type MOSFET 16 controlled by a latch circuit 24 which stores a preceding state, a second input circuit having a lower logic level V<SUB>IL </SUB>made up of a second inverter circuit 23 controlled by an input signal and a P-type MOSFET 15 controlled by a latch circuit which stores a preceding state and the latch circuit 24 which stores a preceding state.
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