| 摘要 |
PROBLEM TO BE SOLVED: To restrain generation of delay variation between the respective cells which is caused by generation of variation of device profile under impact of diffracted light at the time of exposure, imprint, etc., depending on a layout pattern of each standard cell. SOLUTION: In the standard cell S, a p-type and an n-type dummy gate electrodes GAp, GAn which will always be in OFF state are arranged. Gate length of the respective dummy gate electrodes GAp, GAn is prolonged toward the inside of the standard cell S, exceeding end portions of diffusion areas ODp, ODn. Hence, the total surface area and the total perimeter length of gate electrodes of all transistors which were installed in the standard cell S are expanded. As a result, transistor characteristics become almost equality between the respective cells even if variation generates in a profile of a gate electrode of a transistor at a part between the cells S which is caused by impact of diffracted light at the time of exposure, imprint, etc. COPYRIGHT: (C)2005,JPO&NCIPI
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