| 摘要 |
Disclosed is a binary latch that operates as an edge-triggered flip-flop and which is LSSD-testable. The binary latch comprises an edge triggered master flip-flop ( 2 ), with a clock input connected to the system clock (SYS_CLK), with a data input (DI) and with an output (DO), a level sensitive scan design (LSSD) slave latch ( 3 ), connected to the output (DO) of the master flip-flop ( 2 ), a NAND gate ( 4 ) with a first input ( 41 ) connected to the system clock (SYS_CLK), a second input ( 42 ) connected to a test input (TEST) and with an output ( 43 ) connected to the LSSD slave latch clock input (LSSD_clk).
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