| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor memory in which timing control is appropriately conducted to make access to the data in a memory cell. SOLUTION: As a semiconductor memory, a SRAM10 is provided with a memory cell array 11 made of a plurality of memory cells 21 and a timing control circuit 18 which conducts timing control to make access to the data in the memory cells. As dummy circuits, the SRAM10 is provided with dummy word lines DWL and a plurality of dummy cells 22 connected to the dummy word lines DWL and dummy bit lines DBL and XDBL which are used to read data from a dummy cell 22a. Timing signals are generated by a first path which is used to read data from the dummy cell 22a using the dummy bit lines DBL and XDBL and a second path having a different delay characteristic with respect to the first path and either one of the timing signals are used for the timing control of the control circuit 18. COPYRIGHT: (C)2005,JPO&NCIPI
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