| 摘要 |
PROBLEM TO BE SOLVED: To shorten a design time by reducing the number of times of correction of mask layout under the consideration of wiring parasitism in a circuit design stage. SOLUTION: Circuit design based on specifications is performed (S1). A block size is calculated from the calculated value of each element by a block size calculating means for each circuit graphic data of design (S2). A block symbol is prepared from the block size (S3), and the optimal arrangement of all the block symbols is performed (S4), and inter-block symbol connection is performed (S5). The wiring length and wiring parasitism of each wiring is calculated by a wiring parameter calculating means, and the calculation information is stored, and a wiring parasitic database is prepared (S6). The circuit diagram data and the wiring parasitic data and analytic conditions are stored by a circuit simulation means 10, and the circuit simulation is carried out (S7). Mask layout design is performed from the simulation result based on the requested specifications (S8). The influence of the wiring parasitism is analyzed so that the wiring parasitism can be considered in a circuit design stage, and the layout design time can be shortened. COPYRIGHT: (C)2005,JPO&NCIPI
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