发明名称 INSTRUCTION CACHE SYSTEM
摘要 PROBLEM TO BE SOLVED: To provide an instruction cache system for fetching instruction data to be read the next by a central processing unit(CPU) in advance from a program memory in a high speed instruction cache, and for reading the instruction data from the instruction cache, the instruction cache system to prevent the mishit of instruction data in the instruction cache whose capacity is small and to improve the performance of a microprocessor. SOLUTION: An instruction cache 1-2 is constituted of two faces, and while the instruction data are being fetched from one face by a central processing unit(CPU), the instruction data of the next program are transferred from a main storage program memory 1-6 to the other face, and those faces are alternately switched according to the switching of switches 1-3 and 1-4, and the instruction fetch and the transfer of the instruction data of the next program are operated in parallel. Also, the program is divided into a program pieces so as to be fit in the capacity of one face of the instruction cache 1-2, and each program pieces has program-structure in which the execution can be completed within the program piece. COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2005266997(A) 申请公布日期 2005.09.29
申请号 JP20040075648 申请日期 2004.03.17
申请人 FUJITSU LTD 发明人 TOYOYAMA TAKESHI
分类号 G06F12/08;G06F9/38;(IPC1-7):G06F12/08 主分类号 G06F12/08
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