发明名称 Memory module with parallel testing
摘要 Each memory chip of a memory module tests a total of N data bits from X memory blocks for efficient testing and outputs N/X test data bits from one of the memory blocks. A memory module includes a plurality of memory chips and a plurality of comparison units. Each comparison unit is disposed within a respective memory chip for testing a plurality of test data bits from a plurality of memory blocks. In addition, each comparison unit outputs test data bits from one of the memory blocks within the respective memory chip.
申请公布号 US2005216809(A1) 申请公布日期 2005.09.29
申请号 US20050086059 申请日期 2005.03.22
申请人 KIM YOUN-CHEUL;CHOI HEE-JOO;HA KAE-WON;LEE JOON-HEE 发明人 KIM YOUN-CHEUL;CHOI HEE-JOO;HA KAE-WON;LEE JOON-HEE
分类号 G01R31/28;G06F11/00;G06F12/16;G11C29/00;G11C29/28;G11C29/34;G11C29/40;(IPC1-7):G11C29/00 主分类号 G01R31/28
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