Method for fabricating gate electrodes in a field plate trench transistor, and field plate trench transistor

摘要

A method for fabricating gate electrodes ( 7 ) in a field plate trench transistor ( 1 ) having a cell array with a plurality of trenches ( 3 ) and a plurality of mesa regions ( 8 ) arranged between the trenches comprises the following steps: application of a gate electrode layer ( 7 ) to the cell array in such a way that the gate electrode layer ( 7 ) has depressions within or above the trenches ( 3 ), application of a mask layer ( 10 ) to the cell array, etching-back of the mask layer ( 10 ) in such a way that mask layer residues ( 10 ) remain only within the depressions of the gate electrode layer ( 7 ), and etching-back of the gate electrode layer ( 7 ) using the mask layer residues ( 10 ) as an etching mask in such a way that gate electrode layer residues ( 7 ) remain only within/above the trenches ( 3 ).