| 摘要 |
PROBLEM TO BE SOLVED: To simplify control and reduce the number of gates thereby decreasing the cost by controlling a common processing block in a small number of bits when common processing block are provided. SOLUTION: A clock control section 122 is controlled by control signal in two bits from a decoder 121, and to a compression processing section 123, a common processing section 124 and an expansion processing section 125, clocks CLKA, CLKB, CLKC for operating those sections and image data in 8 bits are given, respectively. In the control signal in 2 bits, for example, "00" indicates compression, "01" denotes expansion and "11" shows all clear. When the decoder 121 outputs "00" to the control section 122 by an instruction from a CPU 120, the clocks CLKA, CLKB are respectively supplied to the compression processing section 123 and the common processing section 124, both the sections are activated to compress image data and give the compressed image data to a selector 127, and finally a memory 132 stores the resulting data. In the case of expansion, reverse operations to above are executed. COPYRIGHT: (C)2005,JPO&NCIPI
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