发明名称 |
Parallel operation processor |
摘要 |
A processor having a plurality of processing elements and a decoder operable to decode an instruction. Each of the plurality of processing elements includes: a transfer pattern storage unit operable to store a transfer pattern value that indicates a processing element from which data is transferred; a transfer unit operable to perform a data transfer from the processing element indicated by the transfer pattern value; and an update unit operable to update the transfer pattern value stored in the transfer pattern storage unit, in accordance with a result of decoding a latest instruction by the decoder.
|
申请公布号 |
US2005216699(A1) |
申请公布日期 |
2005.09.29 |
申请号 |
US20050054049 |
申请日期 |
2005.02.09 |
申请人 |
TANAKA TAKESHI;NISHIDA HIDESHI;HOSHINO MASASHI;FURUTA TAKESHI |
发明人 |
TANAKA TAKESHI;NISHIDA HIDESHI;HOSHINO MASASHI;FURUTA TAKESHI |
分类号 |
G06F9/318;G06F9/38;G06F15/00;G06F15/80;(IPC1-7):G06F15/00 |
主分类号 |
G06F9/318 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|